An EEPROM, or electrically-erasable and programmable ROM, uses field effect transistors with a floating gate structure in which a programmed charge can be stored on an electrically isolated floating gate to control the threshold voltage V.sub.T. A read operation differentiates between the impedance presented by a charged (high V.sub.T) gate and an uncharged (low V.sub.T) gate, thereby differentiating between logic states of the memory cell. EEPROMs are erasable cell-by-cell, or in a flash-erase mode in which the entire memory array is erased.
EEPROMs use either of two charge transfer mechanisms for programming--Fowler-Nordheim tunneling or hot carrier injection. Fowler-Nordheim tunneling is generally used for erase operations. EEPROMs using hot carrier injection for programming typically employ FAMOS or floating-gate, avalanche-injection MOS, although hot carrier injection results from channel hot electrons as well as avalanche breakdown (assuming NMOS).
Both charge transfer mechanisms have advantages and disadvantages. Programming an EEPROM memory cell by hot carrier injection requires lower voltage than does Fowler-Nordheim tunneling. On the other hand, the higher voltages required for Fowler-Nordheim tunneling can be generated on-chip because of the very low tunneling current requirements for programming. In contrast, an additional power supply is required for FAMOS-type EEPROMs because of high programming current requirements. Moreover, floating gate erasure using injection of hot holes is disadvantageous in that these carriers can damage the oxide insulator layer, eventually leading to cell degradation and failure. Using a Fowler-Nordheim tunnel current to erase a floating gate results in significantly less damage to the tunnel window oxide, and therefore is advantageous in terms of memory cell durability and reliability.
EEPROMs using hot carrier injection for programming and Fowler-Nordheim tunneling for erasure have been described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee, et al., IEDM 1985 (p. 616-619), (b) "An In-System Reprogrammable 256K CMOS Flash Memory", V. N. Kynett, et al., ISSCC 1988 (p. 132-133), and (c) "A 128K Flash EEPROM using double polysilicon Technology", George Samachisa et al., ISSCC 1987 (p. 87-88). These EEPROMs employ conventional architecture where the drains of two memory cells share one contact. FAMOS gate oxide thickness is a trade-off between adequate tunneling current for erase in a reasonable time, and the impact on yields/reliability from processing defects. That is, thick gate oxide improves process yields/reliability, but reduces tunnel current leading to long erase times. Moreover, gated junction breakdown voltage is degraded with thin gate oxide, so that, during erase, excessive junction leakage (and the unwanted generation of hot carriers) can occur before the onset of adequate Fowler-Nordheim tunnel erase current. (See, Reference (b) and (c)) Thus, these EEPROMs are erased, in part, by hot holes because of low field plate breakdown voltage of the FAMOS source junction.
The approach in Reference (c) uses channel oxide of about 200 Angstroms, and uses channel hot electron injection for programming, and Fowler-Nordheim tunneling for erasure from the same junction. It has two disadvantages: (i) the junction optimization requirements for erasing/programming are incompatible, and cannot be met by the same junction; and (ii) a gate oxide thickness of 200 Angstroms does not allow adequate Fowler-Nordheim tunneling current for reasonable erase times with conventional 12.5 volt EEPROM power supplies. As a result, junction breakdown assisted erase can occur, leading to excessive substrate current during erase.
Thus, EEPROMs, heretofore, have not combined hot carrier injection programming with strictly Fowler-Nordheim tunnel erasing. One problem is that the higher voltages required by Fowler-Nordheim tunnel erasing lead to source junction field plate breakdown, and the unwanted generation of hot carriers. The related application Ser. No. 07/219,529, discloses a memory cell configuration in which a Fowler-Nordheim tunnel window is located on a side of the source opposite the channel, and the junction under the tunnel window terminates under a relatively thick oxide thereby improving source junction field plate breakdown.
Accordingly, a need exists for an EEPROM that is programmed using only hot carrier injection, and is erased using only Fowler-Nordheim tunneling, in a contact-less array configuration. Such an EEPROM would take advantage of the relatively low voltage required for hot carrier injection programming while avoiding channel insulator damage due to hot hole erasure, thereby improving the durability and reliability of the memory cell, and the reduced number of array contacts would provide improved process yields (further improving reliability). In general, a satisfactory memory cell of this type would provide careful control over the channel and junction profile to achieve optimum efficiency for the hot carrier injection programming operation.